In selected micro-processors, some of which require high speed registers as local storage, it would be desirable if each register can be separately addressable from a multiplicity of data-in ports for a write and separately addressable to a multiplicity of data-out ports for a read. The data, in the register, thus would be addressable at any data-in port and readable at any data-out port. Such multi-port devices might comprise three bit memory configurations, arranged with independent read and write addressing, so that upon a write, the identical information is written into each configuration, in the identical address position, and then sequential writes will write into the different port addresses, in parallel, so that each of the three configurations contain the same information in the same address positions, then a simultaneous read of the three configurations in three different positions--three different addresses--will present three different words to each of the three different out ports. When an attempt is made to merge the information and read it from a single configuration problems arise. One such problem, with such arrangements, is that there is no restriction which prohibits all three read heads from trying to read data from the same cell at the same time. Since some of the cells must be significantly larger because of the simultaneous read, the cell size and the array size is double or triple; thus, such multi-port circuits have generally been avoided. Until the present invention, there has been no satisfactory way of preventing multiple reads in a single cell while delivering that cell data to each port with a multiple read.